Extended-Range Second-Order Incremental Sigma-Delta ADC

A single-stage two-steps Extended-Range Second-Order Incremental ADC in 0.13um CMOS technology is presented here which achieves a Signal-to-Noise and Distortion Ratio (SNDR) as large as 73 dB. The proposed architecture of Extended-Range ADC based on Second-order multi-bit CIFF Incremental ADC reuses the IADC structure for coarse (input signal) as well as fine (residue) quantization without need of employment of explicit second ADC thereby minimizing power consumption and area occupancy. With a clock frequency of 80 MHz, the complete ERADC achieves in extracted simulation a peak SNDR of 73 dB at a data rate of 3.2 MS/s (25 clock cycles per conversion).A single-stage two-steps Extended-Range Second-Order Incremental ADC in 0.13um CMOS technology is presented here which achieves a Signal-to-Noise and Distortion Ratio (SNDR) as large as 73 dB. The proposed architecture of Extended-Range ADC based on Second-order multi-bit CIFF Incremental ADC reuses the IADC structure for coarse (input signal) as well as fine (residue) quantization without need of employment of explicit second ADC thereby minimizing power consumption and area occupancy. With a clock frequency of 80 MHz, the complete ERADC achieves in extracted simulation a peak SNDR of 73 dB at a data rate of 3.2 MS/s (25 clock cycles per conversion)